1. Field of the Invention
The present invention relates to a test structure and a test method utilizing the test structure, and, particularly, to a test structure and a test method for wafer level reliability (WLR).
2. Description of the Prior Art
In a semiconductor manufacturing industry, the lifetime test can be generally categorized into two types, called “product reliability” and “process reliability” respectively. The product reliability means that a produced and preliminarily packaged chip is tested in a high temperature, a high pressure and a high humidity state for obtaining the lifetime. The process reliability means that a preliminarily produced semiconductor element is subjected to a lifetime test aimed at a semiconductor element material for ensuring no reliability problems in a successive process.
The reliability test methods in a semiconductor manufacturing industry can be also categorized into two types, “Wafer-Level Reliability (WLR)” and “Package-Level Reliability (PLR)”. The differences between the two test types include that, in the former, the wafer is directly placed in a test machine on a common producing line for a test, and, in the latter, the wafer must be cut into chips and the chips are packaged to form test samples (device under test, DUT), then the samples are socketed into a burn-in board and placed in a high temperature oven (such as up to 350° C.) for a test. The WLR method is generally fast and direct. In the WLR method, the test result can be obtained in a very short time, not after packing, to determine the reliability of the given wafer for subsequent improvements or processes. While, the PLR method needs a long test time. If the test result is not satisfied, it often takes a long time to obtain a next test result, due to the time consumed for packing and re-testing the further modified product.
One of basic reliability tests is the electron migration (EM) test. The EM means that when a conducting wire (e.g. an aluminum wire) connecting transistors is provided with a current for a long time, the aluminum atoms are moved from a negative electrode to a positive electrode by an electron wind force. A depletion of the aluminum atoms in the negative electrode occurs to cause the circuit to open, or a stacking of the aluminum atoms in the positive electrode occur to cause the circuit to short. As time goes on, the aforementioned conditions become serious and finally the integrated circuit doesn't operate. Hence, the EM test is a basic and important test item.
A traditional EM test of a metal is carried out by PLR, in which the test conditions are close to the use condition of the metal, and is widely accepted in the semiconductor industry. Nevertheless, if the test time of PLR-EM test can be shorten with the WLR-EM test, it will be a great help to shorten the manufacturing time. However, such EM test is not generally used in the industry, and the main reason is that some arguments are still pending. First, with respect to the failure mechanism of EM, since the test current density in EM is very high (for example, 60 to 70 mA) and may be ten-folds of that used in the traditional PLR-test, the aluminum wire may be melted away and open due to the high temperature, but not EM. Second, whether the results of WLR-EM test and the traditional PLR-EM test are in good correlation. If the correlation is poor, the test result of WRL-EM may not be correct.
Therefore, there is still a need for a better wafer level test structure and a better wafer level test method for conveniently obtaining test results.